1. Field of the Invention
This invention relates generally to computer timing control circuits and more particularly to a system and method for using an improved half-clock design module to implement computer timing control circuitry.
2. Description of the Prior Art
Processing speed is a critical feature in most computer systems and is thus an important consideration for both computer users and computer manufacturers. A computer system with a faster processing speed is generally able to produce more work-product than a system having a slower processing speed, so modern computing systems are typically designed with maximum processing speed as an important engineering goal.
Computer processing speeds are significantly affected by the computer system's clock frequency, with higher clock frequencies usually resulting in higher processing speeds. In general, a clock signal is distributed to the various electronic circuits within a computer system to control timing of the system's digital signals and thereby synchronize the computing process. Typically, the clock signal consists of a series of digital pulses having a specified frequency and specified voltage levels. Each clock pulse has a rising edge and a falling edge, however, conventional computer systems and design synthesis tools typically utilize only the rising edge of the clock pulse to synchronize the computer's digital signals.
Attempts to achieve higher clock speeds have conventionally utilized clock-doubler devices. FIG. 1 shows a conventional prior art clock doubling system. A prior art system clock 10 provides to clock doubler 14 a CLK.times.1 signal 12 which is converted into a second CLK.times.2 signal 16 having twice the frequency of CLK.times.1 signal 12. CLK.times.2 signal 16 is then provided to the appropriate prior art computer circuitry 18 to clock the system at the doubled rate. Only one edge of the doubled clock signal is typically used to clock the digital circuitry.
Higher clock rates effectively speed up processing time, but increased clock frequencies also can significantly increase power consumption. The increased power consumption is primarily due to the increased electrical current drawn during the greater number of clock transitions between high and low digital voltage states. This increased power consumption results in higher computer operation costs. In battery-powered systems, such as notebook computers, increased power consumption also reduces battery life. High-speed computer systems which use a clock doubler also must determine and minimize the skew between the doubled clock signal and the system clock signal. If the skew is very long or indeterminate, it may be difficult to keep the clock doubler and the system clock tightly synchronized.
Clock-doublers have another economic impact on the cost of implementing a computer system. Clock-doubling circuitry typically requires a number of additional electrical components and associated circuitry, which add to the expense of implementing the computer system. Further, clock-doublers are a relatively inflexible way to speed up computer processing. During the computer design process, design engineers may require a specialized timing control device to control a smaller subsection of the computer electronics. Clock doublers typically use an "all or nothing" approach in which a single clock doubler device generates a doubled clock signal which then performs the clocking functions for all of the computer circuitry. This approach makes it difficult to use a clock doubler to selectively supply timing pulses to individual circuits within the computer electronics.
Although a clock doubler effectively doubles the system clock frequency, computer systems which feature clock doublers still typically utilize only one edge of the doubled clock signal to control timing of the digital circuitry. It would be useful to use either edge of the system clock signal to control generating a signal, and then to use the generated signal to control selected computer circuitry.
Therefore, an improved system and method is needed to economically implement computer timing control circuitry using an improved half-clock design module.